1. Field of the Invention
The present invention relates to a power converter with feed-forward voltage compensation for enabling a power factor correction (PFC) circuit and a method thereof and, more particularly, to a power converter capable of activating a PFC circuit under the same input power condition and a method thereof.
2. Description of Related Art
According to the international standard IEC1000-3-2, the PFC circuit has to be activated to perform the power factor correction and boost procedure before the input power of a power converter with a PFC circuit reaches 75 W. In order to achieve the object of power saving, it is necessary for a power converter with a PFC circuit to close the action of the PFC circuit under a light load. The use of a PFC circuit is a well-known art in the field of the power converters. The PFC circuit is used to reduce the current harmonic at the power source of power converters so as to make the power factor of the input power of the power converters close to 1. Moreover, the PFC circuit also has the function of boosting voltage.
FIG. 1 is a circuit diagram of a conventional power converter with a PFC circuit. A power converter 1 comprises a PFC circuit 10, a power stage 20, a feedback unit 30 and a comparator 40. The PFC circuit 10 comprises a PFC converter 102, a PFC controller 104 and a bus capacitor CB. The power stage 20 comprises a PWM converter 202 and a PWM controller 204.
The PFC converter 102 is controlled by the PFC controller 104 of the PFC circuit 10 in response to an input voltage VIN. A bus voltage VBUS is built on the bus capacitor CB after the power factor correction and boost procedure are finished. The PWM converter 202 in the power stage 20 is to convert the bus voltage VBUS to an output voltage VOUT for a load.
As shown in FIG. 1, the feedback unit 30 receives a feedback voltage VFB in proportional to the load of the power stage 20. The feedback voltage VFB has a higher level under a heavy load and the feedback voltage VFB has a lower level under a light load. At the output of the power converter 1, the feedback voltage VFB and the input power increase once the load gradually rises from a light load to a heavy load. Under the requirement of the international standard IEC1000-3-2, the power converter 1 has to activate the PFC circuit 10 before the input power of the power converter 1 reaches 75 W.
The negative input of the comparator 40 receives a reference voltage VT, and positive input of the comparator 40 receives the feedback voltage VFB. The comparator 40 can be implemented by a hysteresis comparator. When the load of the power converter 1 is larger than the upper limit of the hysteresis range of the comparator 40, the comparator 40 generates a control signal SC in a high-level to drive the PFC controller 104. The PFC controller 104 generates a PFC drive signal SPFC in a high-level to the PFC converter 102, which then activates the power factor correction and boost procedure. Meanwhile, the input voltage VIN stored at the bus capacitor CB instantaneously rises to a high DC level, and the feedback voltage VFB drops relatively. When the load of the power converter 1 decreases and the feedback voltage VFB drops to below the lower limit of the hysteresis range of the comparator 40, the comparator 40 then outputs a control signal SC in a low-level to drive the PFC controller 104. The PFC controller 104 generates a PFC drive signal SPFC in a low-level to the PFC converter 102, which then closes the power factor correction and boost procedure.
Reference is made to FIG. 1 again. When the power switch Q in the power stage 20 is on, the energy WIN stored in the magnetizing inductance LP of the transformer T can be represented by,
                              W          IN                =                                            1              2                        ×                          L              P                        ×                          I              P              2                                =                                    P              IN                        ×                          T              S                                                          (        1        )            wherein the primary-side switching current IP flowing through the primary side of the transformer T can be represented by,
                              I          P                =                                            V              IN                                      L              P                                ×                      t            on                                              (        2        )            The feedback voltage VFB will influence the primary-side switching current IP under the normal load. The magnitude of the primary-side switching current IP depends on the load. Therefore, the feedback voltage VFB is in proportional to the magnitude of the load. The output power increases and the feedback voltage VFB has a higher level under the heavy load. The output power decreases and the feedback voltage has a lower level under the light load.
The maximum input power PIN is obtained by substituting (2) into (1),
                              P          IN                =                                                            L                P                                            2                ×                                  T                  S                                                      ×                          I              P              2                                =                                                    V                IN                2                            ×                              t                on                2                                                    2              ×                              L                P                            ×                              T                S                                                                        (        3        )            In Equations (1) to (3), ton is on-time of a PWM control signal VPWM when the power switch Q is on, and TS is the switching period of the PWM control signal VPWM.
The conventional power converter 1 controls the PFC circuit 10 by means of the feedback voltage VFB and the hysteresis range of the comparator 40 to perform the power factor correction and boost procedure. When the feedback voltage VFB rises to the upper limit of the hysteresis range, the PFC circuit 10 performs the power factor correction and boost procedure. The PFC circuit 10 closes the power factor correction and boost procedure once the feedback voltage VFB drops to the lower limit of the hysteresis range. The feedback voltage VFB has a lower level when the input voltage VIN is high (VH). The PFC circuit 10 usually activates the power factor correction and boost procedure only when the input power of the power converter 1 is larger than 75 W.
FIG. 2 is a curve showing the relation between the input voltage and the input power of a conventional power converter 1 when the PFC circuit is activated. From Equation (3), we know that the input power PIN of the power converter 1 is in proportional to the square of its input voltage VIN. Therefore, the power converter 1 has to reach a larger input power PINH to control the PFC circuit 10 to enabling the boost procedure once the load is heavy and the input voltage VIN (VH) is high.
Because the conventional power converter 1 activates the PFC circuit 10 only when the input power is larger than 75 W under the conditions of high input voltage VH (larger than 180 Vac) and heavy load (larger than 150 W). Hence, the requirement of the international standard IEC1000-3-2 cannot be satisfied.